Nano Electronic Materials and Devices

Part of the Micro-Nanoelectronics Centre


As the minimum dimensions of devices are reduced to 20nm and below, however, the use of classical device architecture ad classical materials is no longer possible. Furthermore, the use of silicon-based devices is expanding from digital circuits to systems that comprise logic gates, analogue functions, sensor, actuators and micromechanical components.

Developments in the field of information and communication technologies are driven to a large extent by continuing innovations and scaling of silicon-based complementary metaloxide-semiconductor field effect-transistor (CMOS) technologies.The ability to scale the minimum dimensions of MOS based field effect transistors (MOSFETs), without changing the basic materials (Si and SiO2) and the essential device structure has been the main driving force behind the dramatic progress in the performance of integrated circuits.

The activities of the Nano Electronic Materials and Devices Group focus on:

  • High-k Research: 
    The incorporation of high-k oxides into MOSFET and integrated capacitors as we enter the “materials era” of device scaling is a major challenge. Devices requiring the introduction of high-k are:-
    • MOSFET devices: Controlling the structural and electronic properties of the interfacial region between the high-k films and high mobility Ge or III-V substrates, as well as integrating these devices onto silicon wafers
    • Integrated capacitors in memories and analog applications: For memories the challenge is improving the capacitance per unit area while maintaining leakage levels < 1x10-8 A/cm2. Analog applications involve the use of thick high-k layers (>50nm), along with the understanding and control of the capacitance variation with voltage, temperature, and frequency.
  • Ultimate Silicon Devices:
  • The research in this group focuses on the modeling, fabrication and characterization of nanowire multiple-gate MOS transistors. The multiple-gate structure allows for the shrinking of MOS transistors in the sub-decananometer regime.

The group head is Dr. Paul Hurley.


Dr. Paul Hurley
Senior Research Scientist
Tyndall National Institute
Lee Maltings Complex
University College Cork, Cork, Ireland
Tel: +353 21 490 4080

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